? semiconductor components industries, llc, 2009 december, 2009 ? rev. 10 1 publication order number: mc74hc138a/d mc74hc138a 1-of-8 decoder/ demultiplexer high ? performance silicon ? gate cmos the mc74hc138a is identical in pinout to the ls138. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hc138a decodes a three ? bit address to one ? of ? eight active ? low outputs. this device features three chip select inputs, two active ? low and one active ? high to facilitate the demultiplexing, cascading, and chip ? selecting functions. the demultiplexing function is accomplished by using the address inputs to select the desired device output; one of the chip selects is used as a data input while the other chip selects are held in their active states. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 100 fets or 29 equivalent gates ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 1 16 pdip ? 16 n suffix case 648 1 16 1 16 1 16 mc74hc138an awlyywwg 1 16 hc138ag awlyww hc 138a alyw 1 16 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g = pb ? free package = pb ? free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on p age 2 of this data sheet. ordering information 1 16 74hc138a alywg soeiaj ? 16 f suffix case 966 1 16
mc74hc138a http://onsemi.com 2 7 y6 y5 y4 y3 y2 y1 y0 y7 9 10 11 12 13 14 15 3 2 1 cs1 cs2 a0 a1 a2 active-low outputs address inputs cs3 chip- select inputs 5 4 6 pin 16 = v cc pin 8 = gnd inputs outputs cs1cs2 cs3 a2 a1 a0 y0 y1 y2 y3 y4 y5 y6 y7 x x h xxxhhhhhhhh x h x xxxhhhhhhhh l x x xxxhhhhhhhh h l l lll lhhhhhhh h l l llhhlhhhhhh h l l lhlhhlhhhhh h l l lhhhhhlhhhh h l l hllhhhhlhhh h l l hlhhhhhhlhh h l l hhlhhhhhhlh h l l hhhhhhhhhhl function table h = high level (steady state); l = low level (steady state); x = don?t care figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 a0 cs2 a2 a1 y7 cs1 cs3 gnd y3 y2 y1 y0 v cc y5 y4 y6 figure 2. logic diagram ordering information device package shipping ? mc74hc138ang pdip ? 16 (pb ? free) 500 units / rail MC74HC138ADG soic ? 16 (pb ? free) 48 units / rail mc74hc138adr2 soic ? 16 2500 tape & reel mc74hc138adr2g soic ? 16 (pb ? free) 2500 tape & reel mc74hc138adtr2 tssop ? 16* 2500 tape & reel mc74hc138adtr2g tssop ? 16* 2500 tape & reel mc74hc138afg soeiaj ? 16 (pb ? free) 50 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74hc138a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip? soic package? tssop package? 750 500 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip, soic or tssop package) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ?derating ? plastic dip: ? 10 mw/ c from 65 to 125 c soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 .w/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 2) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc138a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ? 55 c to 25 c 85 c 125 c v ih minimum high ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 ???? ????????? ???????? ??? ?????? ??? ???? ??? ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter v cc v guaranteed limit unit ? 55 c to 25 c 85 c 125 c t plh , t phl maximum propagation delay, input a to output y (figures 1 and 4) 2.0 3.0 4.5 6.0 135 90 27 23 170 125 34 29 205 165 41 35 ns t plh , t phl maximum propagation delay, cs1 to output y (figures 2 and 4) 2.0 3.0 4.5 6.0 110 85 22 19 140 100 28 24 165 125 33 28 ns t plh , t phl maximum propagation delay, cs2 or cs3 to output y (figures 3 and 4) 2.0 3.0 4.5 6.0 120 90 24 20 150 120 30 26 180 150 36 31 ns t tlh , t thl maximum output transition time, any output (figures 2 and 4) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns c in maximum input capacitance ? 10 10 10 pf c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 55 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc138a http://onsemi.com 5 figure 1. 50% t phl t plh v cc gnd figure 2. valid valid output y 50% t f t r v cc gnd t plh t tlh 90% 50% 10% output y input cs1 t phl 90% 50% 10% t thl input a switching waveforms t thl t tlh v cc gnd t r t phl t plh output y input cs2, cs3 90% 50% 10% 90% 50% 10% figure 3. t f *includes all probe and jig capacitance figure 4. test circuit c l * test point device under test output pin descriptions address inputs a0, a1, a2 (pins 1, 2, 3) address inputs. these inputs, when the chip is selected, determine which of the eight outputs is active ? low. control inputs cs1, cs2, cs3 (pins 6, 4, 5) chip select inputs. for cs1 at a high level and cs2, cs3 at a low level, the chip is selected and the outputs follow the address inputs. for any other combination of cs1, cs2, and cs3, the outputs are at a logic high. outputs y0 ? y7 (pins 15, 14, 13, 12, 11, 10, 9, 7) active ? low decoded outputs. these outputs assume a low level when addressed and the chip is selected. these outputs remain high when not addressed or the chip is not selected.
mc74hc138a http://onsemi.com 6 a0 a1 a2 cs3 cs2 cs1 1 2 3 4 5 6 15 14 13 12 11 10 9 7 y1 y2 y3 y4 y5 y6 y7 y0 expanded logic diagram
mc74hc138a http://onsemi.com 7 package dimensions pdip ? 16 n suffix case 648 ? 08 issue t soic ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc74hc138a http://onsemi.com 8 package dimensions tssop ? 16 dt suffix case 948f ? 01 issue a ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n
mc74hc138a http://onsemi.com 9 package dimensions soeiaj ? 16 f suffix case 966 ? 01 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74hc138a/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
